Integrated circuit devices (or chips) typically comprise a silicon substrate and semiconductor elements, such as transistors, formed from doped regions within the substrate. Interconnect structures, formed in parallel layers overlying the semiconductor substrate, provide electrical connection between elements to form electrical circuits. Typically, several (e.g., 6–9) interconnect layers (referred to as “M” layers or metallization layers) are required to interconnect the doped regions and elements of the integrated circuit device. The process of forming the interconnects between devices is referred to as metallization and is performed using a number of photolithographic, etching and deposition techniques. Generally, the interconnect structures comprise a plurality of stacked conductive layers substantially parallel to the upper surface of the substrate and vertical conductive plugs that interconnect the stacked conductive layers. The top metallization layer provides attachment points for conductive interconnects (e.g., bond wires) for connecting the device to pins or leads of a package structure.
An exemplary semiconductor structure and the associated metallization or interconnect layers are illustrated beginning in a FIG. 1 cross-section, where an n-type MOSFET 8 is formed within a silicon substrate 10, comprising a p-type well 11, lightly doped (n−) source/drain regions 12/14, source/drain regions (n+) 16/18, and a polysilicon gate 20 formed over a gate oxide 22. Oxide spacers 24 are formed on the sides of the polysilicon gate 20. Silicon dioxide isolation regions 32 isolate adjacent devices formed within the silicon substrate 10.
An intermetal dielectric layer 40 is formed over an upper surface 42 of the silicon substrate 10, followed by formation of windows 44 extending through the intermetal dielectric layer 40 to the device regions that are to be connected to other active regions formed in the substrate 10. The windows 44 are formed using known photolithographic masking, patterning and etching processes. Tungsten plugs, formed within the windows 44 as described below, interconnect the device regions to an overlying interconnect layer formed later overlying the upper surface of the intermetal dielectric layer 40.
As illustrated in FIG. 2, a titanium layer 50 is deposited in the windows 44 and a field region 52, i.e., the upper surface of the intermetal dielectric layer 40. Within the windows 44, the titanium layer 50 reacts with the underlying silicon (of the source/drain regions 12/14 and the polysilicon gate 20) to form a localized titanium silicide region within the silicon. This silicide region provides improved conductivity between the active region of the device and the tungsten plugs that are formed later in the windows 44.
According to one embodiment, the titanium layer is about 500 Angstroms thick in the field region 52, with about 50% step coverage along a bottom surface 54 of the windows 44, and about 10% step coverage on sidewalls 56 of the windows 44. Step coverage is a measure of the material thickness as a percent of the thickness in the field region 52. Thus the titanium thickness along the bottom surface is about 250 Angstroms, and the thickness along the sidewalls 56 is about 50 Angstroms. When used for the upper level metallization layers the titanium layer is only about 300 Angstroms thick as there is no underlying silicon layer with which to form a silicide region.
During the semiconductor fabrication process it is sometimes advantageous to include an adhesion layer between two dissimilar material layers that may not adequately adhere to each other. This adhesion or “glue” layer promotes layer bonding by forming an intermetallic bond with the underlying and overlying layers. Thus the titanium layer 50 also serves as an adhesion layer for a titanium-nitride layer formed thereover according to the next process step described below.
Next a titanium-nitride (TiN) layer 58 is deposited. The TiN layer serves as a barrier between the underlying titanium layer and the fluorine-based gas used for depositing the tungsten as described below, as the fluorine-based gas is highly reactive with titanium. In one embodiment the titanium-nitride layer 58 is about 400 Angstroms thick in the field region 52, with about 50% step coverage on the bottom surface 54 and about 10% step coverage on the sidewalls 56.
It is known that titanium-nitride can delaminate from oxide-based materials such as the intermetal dielectric layer 40. Thus use of the titanium layer 50 is advantageous to promote adhesion between the titanium-nitride layer 58 and the underlying dielectric material of the field region 52 and of the sidewalls 56.
During the semiconductor fabrication process it is advantageous to perform consecutive processing steps within the same process tool to avoid exposing the wafer to ambient contaminants and moisture. Thus according to conventional processing, the titanium and the titanium-nitride of the titanium layer 50 and the titanium nitride layer 58 are deposited in different chambers of the same physical vapor deposition (PVD) (also referred to a sputtering) process tool.
As shown in FIG. 3, a tungsten layer 60 is formed in the windows 44 and in the field region 52 by a chemical vapor deposition process involving tungsten hexafluoride (WF6) and silane (SiH4). The silicon substrate 10 then undergoes a chemical-mechanical polishing step, leaving tungsten plugs 62 within the windows 44. See FIG. 4.
According to FIG. 5, an aluminum stack 66 (also referred to as the first metallization layer or M1) comprising, from bottom to top, a titanium layer, a titanium nitride layer, an aluminum layer and an anti-reflective cap layer, is deposited over the field region 52. The individual layers of the aluminum stack 66 are not shown in FIG. 5. The titanium and the titanium-nitride layers of the aluminum stack 66 serve the same purposes as the titanium and titanium nitride layers 50 and 58 as described above, but are typically thinner because there is no silicide region formed with the titanium layer, as there is no underlying silicon at this level.
Certain regions of the aluminum stack 66 are removed using conventional masking, patterning and etching steps, leaving the desired first level interconnect structure, comprising regions 66A, 66B and 66C, in the pattern required for interconnecting the device regions formed in the silicon substrate 10. See FIG. 6.
Also as shown in FIG. 6, an intermetal dielectric layer 70 is formed over the first level metallization layer 66 to insulate the latter from an overlying second level interconnect structure to be subsequently formed. Before the second level interconnect is formed, a chemical/mechanical polishing process is performed to planarize an upper surface 72 of the intermetal dielectric layer 70. The resulting structure is illustrated in FIG. 7.
As shown in FIG. 8, via openings 76 are formed in the intermetal dielectric layer 70 using conventional photolithographic patterning, masking and etching steps. Tungsten plugs 80A and 80B, shown in FIG. 9, are formed in the via openings 76 to electrically contact regions of the underlying first metallization level 66. Specifically, the tungsten plug 80A contacts the interconnect segment 66B and the tungsten plug 80B contacts the interconnect segment 66C. The tungsten plugs 62A and 62B are conventionally formed by chemical-vapor deposition during which tungsten is also deposited on the upper surface or field region 72. Like the tungsten plugs 62 in the first metallization layer 66, the tungsten plugs 80A and 80B include titanium and titanium nitride layers serving the same purpose as the titanium layer 50 and the titanium nitride layer 58 as described above. In addition, the titanium layer promotes bonding of the titanium-nitride layer to the underlying aluminum of the first metallization layer 66.
The substrate 10 undergoes a chemical/mechanical polishing step to remove the tungsten overfill and replanarize the upper surface 72, leaving only the tungsten plugs 80A and 80B. FIG. 9 illustrates the configuration of the substrate 10 following the chemical/mechanical polishing replanarization.
Next an aluminum stack for the second metallization layer (M2) is deposited on the upper surface 72 in electrical contact with the tungsten plugs 80A and 80B. The second metallization layer comprises, from bottom to top, a titanium layer, a titanium nitride layer, an aluminum layer and an anti-reflective cap layer. The individual layers of the aluminum stack 82 are not shown in FIG. 10. The titanium and the titanium-nitride layers serve the same purposes as the titanium and titanium nitride layers 50 and 58 described above, but are typically thinner because there is no silicide region formed with the titanium, as there is no underlying silicon at this level. The second metallization layer is patterned, masked and etched to form the required circuit interconnect structures, identified by reference characters 82A and 82B in FIG. 10.
The process of forming dielectric layers, conductive plugs (e.g., formed of tungsten) and overlying interconnect layers continues as required to implement the interconnections required for the operative integrated circuit device. A passivation layer (not shown) is formed over the final interconnect layer to protect the formed device.
As will be described further below, the various layers formed during the above-described metallization processes, in particular the titanium layers and the titanium-nitride layers, are conventionally formed by a physical vapor deposition process, a process known generally for depositing a material onto a substrate.
An exemplary simplified sputtering process chamber 100, illustrated in FIG. 11, encloses a target 102 formed of the material to be deposited on a wafer 106 positioned on a chuck 107 located near the bottom of the chamber 100. A DC power supply 110 maintains a negative bias on the target 102 with respect to a grounded chamber shielding 108. The chamber 100 is maintained at a vacuum during the sputtering process. Conventionally, argon molecules are introduced into the chamber 100 via an inlet 112 and ionized by the electric field between the target 102 and the chamber shield 108, producing a plasma of positively charged argon ions 116. The argon ions 116 gain momentum as they accelerate toward the negatively charged target 102.
A magnet 118 creates a magnetic field that generally confines the argon plasma to a region 119 where the increased plasma density improves the sputtering efficiency. As the argon ions 116 strike the target 102, the momentum of the ions is transferred to the atoms of the target material, sputtering or knocking the atoms from the target 102. A high density of argon ions 116 in the chamber 100 ensures that a significant number of sputtered atoms condense on the upper surface of the wafer 106. The target material is thus deposited on the wafer 106 without undergoing any chemical or compositional changes. The various sputtering chamber parameters, including chamber pressure, chamber and wafer temperature, deposition power (i.e., the power supplied to the target 102 by the power supply 110, where power is the product of voltage and current) can be varied to achieve the desired characteristics in the sputtered film. Layers of different materials can also be sputtered in a single process using multiple target arrangements.
Since the surface of the wafer 106 typically comprises various non-planar features (e.g., openings, windows, trenches), a deposition process for depositing a conformal layer on the surface and/or within the features must provide good deposition coverage or step coverage as defined above. Sputtering employs a planar source and thus material is sputtered from every point on the target 102, arriving at the wafer 106 over a wide angular range to provide a degree of conformal deposition over these various non-planar features. However, as device sizes shrink, the non-planar features also shrink and good conformal coverage is more difficult to achieve. Advanced sputtering techniques, including ion metal plasma sputtering (to be described below), have been introduced to provide the required conformal coverage.
It is known that the sputtering of material onto a wafer can raise the wafer temperature due to the friction created upon impact of the target atoms or molecules with the wafer. The heat can cause uneven film deposition on the wafer surface. Also, if the wafer temperature is sufficiently high, aluminum from metal interconnect layers can extrude through overlying via openings, especially during the process of depositing barrier layers in the via openings.
One known technique for limiting the wafer temperature and the aforementioned extrusion difficulties is to flow a coolant gas, such as argon or helium, along the wafer backside surface to thermally couple the wafer 106 to the chuck 107 and thus draw heat from the wafer 106 to the chuck 107. To maintain the wafer 106 in position against the force of the coolant gas, a ring-like clamp is positioned over the wafer. In lieu of the clamp, an electrostatic chuck can be employed to maintain the wafer position by an electrostatic force generated by an electric field formed between the wafer and the electrostatic chuck Generally, an electrostatic chuck is more expensive than a clamp-type chuck Also, high-voltage external power supplies are required to charge the wafer 106 and the electrostatic chuck to create the electrostatic forces.